As semiconductor devices become more highly integrated, it may be necessary to decrease a size of a transistor. There may be limitations, however, as to how shallow a junction depth of a source/drain may be formed.
As a channel length decreases from a long channel to a short channel of 0.5 μm or less, a depletion region of the source/drain region may penetrate into the channel to decrease the effective channel length and may decrease the threshold voltage. This may generate a short channel effect of losing a gate controlling function at a MOS transistor.
To prevent the short channel effect, a thickness of the gate insulating layer may be decreased, a channel between the source/drain (e.g. a maximum width of depletion region below the gate) may be decreased, and/or the impurity concentration within the semiconductor substrate may be decreased.
Forming a shallow junction may also be beneficial. To this end, an ion implantation apparatus and a subsequently implemented thermal treatment process to achieve a method for forming the shallow junction during forming semiconductor devices may be beneficial.
A MOS transistor may be a representative of a lightly doped drain (LDD) structure. A MOS transistor may generally be used for a memory semiconductor device (such as a DRAM). A MOS transistor may be a flat type transistor, and may include a gate insulating layer formed on a silicon substrate and a conductive pattern formed on the gate insulating layer.
As a level of integration of a semiconductor device increases, however, a line width of a gate pattern may decrease and a length and width of a channel may also decrease. This may increase a negative effect of the transistor operation such as a short channel effect or a narrow channel effect.
In addition, a drive current of an MOS transistor may flow through a substrate channel below a gate electrode of each cell. As the level of integration of a semiconductor device increases, a size of the device may gradually decrease, and the drive current may flow through a extremely limited depth and width near the gate electrode. Accordingly, an amount of drive current may be extremely limited, and may deteriorate operational characteristics of the transistor.
To address the short channel effect and the drive current limitation problem in the MOS transistor, a pin-type MOS transistor may be used. In a pin-type MOS transistor, an area of the substrate contacting the gate electrode having a shallow junction structure may be enlarged, which may increase the drive current.
A related art transistor of a semiconductor device will be described referring to attached drawings.
FIG. 1 is an example schematic diagram of a related art pin-type MOS transistor and FIG. 2 is an example cross-sectional view taken along the line I-I of the pin-type MOS transistor illustrated in FIG. 1.
Referring to FIGS. 1 and 2, a related art pin-type MOS transistor may include isolation layer 101 formed at an isolation region of semiconductor substrate 100. It may further include active area 105 that may protrude above an upper surface of isolation layer 101 and be formed along one direction. It may further include gate electrode 106 formed along a direction crossing the protruding active area 105, and may have gate insulating layer 130 between them. It may further include source/drain impurity regions formed in active area 105 at sides of gate electrode 106.
Source/drain impurity regions may be formed at active area 105 under gate electrode 106 with a channel region between them.
Gate electrode 106 may cover protruded active area 105, and therefore may be formed on three surfaces of active area 105. Accordingly, a width of gate electrode 106 may increase in an amount approximately equal to a height of the protruded area. This may increase the amount of the drive current when compared to a flat structured MOS transistor.
The related art transistor of the semiconductor device may have various problems.
Referring to FIG. 2, for example, due to divot A that may be generated at a bottom portion of the pin during formation of the related art pin-type MOS transistor, an implementation of subsequent processes, for example, the formation of a uniform gate insulating layer, may be difficult. In addition, because of the thinning phenomenon of the gate insulating layer of portion A, device characteristics may be degraded and a short of the gate insulating layer may occur, which may reduce a reliability of the device.